1. Technical Field
The present invention relates to a digital signal receiving circuit which converts a demodulated signal to a baseband signal in a data transmission system, such as wired and wireless communications system, and more particularly, to DC-potential compensation for a demodulated signal.
2. Description of the Related Art
FIG. 2 is a view showing the configuration of a conventional digital signal receiving circuit.
The digital signal receiving circuit receives an analog signal demodulated in a demodulator circuit as an input signal IN, and regenerates an output signal OUT of the baseband by comparing the input signal IN with a reference potential REF obtained from the input signal IN.
The digital signal receiving circuit includes a peak detector 1 which detects the electric potential at the peak of the waveform of the input signal IN provided from a demodulator circuit (not shown), and a bottom detector 2 which detects the potential at the bottom of the waveform of the input signal IN. A peak level PL outputted from the peak detector 1 and a bottom level BL outputted from the bottom detector 2 are provided across a resistor 5 via buffer amplifiers 3 and 4, respectively. The reference potential REF is thus outputted from the midpoint of the resistor 5.
The reference potential REF is provided to the reference terminal of a comparator (CMP) 6, whereas the input signal IN is provided to the comparison terminal of the comparator 6, so that the output signal OUT is outputted from the output end of the comparator 6.
In the digital signal receiving circuit, the peak detector 1 is configured to maintain the peak level PL by immediately following an offset when the input signal IN rises and by following an offset with a large time constant when the signal input IN drops. The bottom detector 2 is configured contrarily to the peak detector 1 to maintain the bottom level BL by immediately following an offset when the input signal IN drops and by following an offset with a large time constant when the input signal IN rises. As a consequence, an average level of the bottom level BL and the peak level PL is outputted from the midpoint of the resistor 5 as the reference potential REF.
Further, the comparator 6 compares the input signal IN with the reference potential REF, and regenerates a binary baseband signal which indicates either “L” or “H” according to the comparison result. The baseband signal is outputted as the output signal OUT.
Examples of the related art are disclosed, for example, in Japanese Patent Applications (Kokai) No. H10-84231 and No. 2001-36470.
The digital signal receiving circuit configured as above, however, has problems as follows.
FIG. 3 is a signal waveform chart used to describe the problems with the digital signal receiving circuit of FIG. 2.
As is shown in FIG. 3, for example, when a signal with an offset which increases in DC (Direct Current) potential by a certain level is inputted as the input signal IN, the peak level PL outputted from the peak detector 1 rises by immediately following the offset. On the contrary, the bottom level BL outputted from the bottom detector 2 does not follow the offset immediately and is maintained almost at the current level. The reference potential REF therefore does not take the intermediate potential between the peak and the bottom of the actual input signal IN. This makes the digital signal receiving circuit unable to regenerate a correct baseband signal or output the output signal OUT having an abnormal pulse width. In the case of the occurrence of an offset such that reduces the DC potential of the input signal IN by a certain level, the same problem is raised because the peak level PL outputted from the peak detector 1 does not follow the offset.